Applications for this technology are found in communications infrastructure, radar, and electronic surveillance.
The clocks of a time-interleaved ADC system are usually generated on-chip by dividing a high-frequency clock. Ideally, each clock should be uniformly spaced in time: however, due to mismatches in layout and clock generator circuits, the clock edges deviate from the ideal case and cuase timing-skew. Timing-skew is a dominant source of error in time-interleaved ADCs causing reduced accuracy and limiting the frequency operating range.
This invention is a system to detect and calibrate timing-skew in time-interleaved ADCs by incorporating a coarse ADC operating at full sampling rate. Since this coarse ADC is not affected by the timing-skew errors, it can be used as a reference signal, eliminating the need for an additional time reference. The method offers simplified computation, which allows it to achieve high resolution and speed at a reduced the footprint and power consumption. Speeds of 1 GHz have been achieved with the current implementation. Achieving 5 Hz samples/sec is envisioned.
- Achieves high resolutions at high speeds
- Reduced power consumption