Compact and Scalable Phased Array

A phased array is disclosed having a master clock unit (outputting a clock signal for synchronization), a plurality of channel circuits, a micro-controller unit having an interface to communicate instruction(s) to each of the plurality of channel circuits to independently control phase and amplitude of each of the plurality of channel circuits, and a plurality of channel outputs representing channel outputs of all channel circuits. Each channel circuit receives the clock signal from the master clock unit and outputs a channel output, wherein each channel circuit has a phase control unit to control phase of the channel output signal of each channel circuit and a gain control unit to control amplitude of the channel output signal of each channel circuit.