Enhancement-Mode MOS Semiconductor Transistors with High Threshold Voltage

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A field effect transistor that has a source, a drain, a gate, a semiconductor region, and a dielectric region. The dielectric region is located between the semiconductor region and the gate. Negatively charged ions are located within the dielectric layer underneath the gate.

Researchers

Tomas Palacios / Yuhao Zhang

Departments: Dept of Electrical Engineering & Computer Science
Technology Areas: Electronics & Photonics: Semiconductors / Energy & Distribution: Distribution
Impact Areas: Connected World

  • enhancement-mode transistors with increased threshold voltage
    United States of America | Granted | 9,704,959

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