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Problem Addressed

To achieve the high computation speeds that meet the demands of higher functionality in integrated circuits while being pushed into smaller footprints, new packaging structures need to integrate more dies with greater function, higher I/O counts, and smaller die pad pitches. The current solutions for densifying packages are based upon materials selection, package design, and integration approach. This technology identifies material selection, package design, and integration approaches to minimize resistance for a superconducting path between two chips in a flip-chip configuration.