Header and Body 4


  • Enhanced system capabilities as well as reduced size, weight, power, and cost
  • Significant reduction in the length of metal interconnect lines yielding increased circuit speed, decreased power loss
  • Increased freedom in mixing technologies and materials without compromising performance, widening the design space for this device
  • Eliminates the need for through silicon via, decreased chip fragility
  • Increased Package-on-Package (PoP), embedded active circuit densities
  • Presents the possibility for use in wafer level packaging (WLP)