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This technology presents an approach to provide the thinnest possible active area cross section for a multi-tier, flip-chip capable, hybrid, 3D Integrated Circuit containing multiple SOI and non-SOI technologies. It uses microbump technology capable of creating single bumps for finer pitch structures or multiple bump arrays for larger pitch structures to minimize solder volume and spreading. The microbump technology minimizes the possibility of electrical shorts so the circuit is still functional. The interconnects consist of microbump and under-bump metallurgy where microbumps react with the under-bump at the interface to create a lower temperature melt interface. This interface melts at a lower temperature than the original bump materials, which makes it possible to create interconnects that can be reworked as double assembly and maintain reliable contact. These devices and circuit elements can be operated at low temperature to provide for reduced operating voltages, higher speed operation, and low power dissipation.