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This technology covers multilayer semiconductor devices and methods for fabricating a multi-layer semiconductor structures. A simultaneous fabrication of building blocks, and subsequent alignment, joining and interconnection through a via last or via first process generates a multi-layer semiconductor structure. This fabrication approach provides the thinnest possible active area cross section for a multi-tier, flip-chip capable, hybrid, 3DIC. Thin cross-sections lead to lighter and slimmer 3D structures, so packaging can be more efficient. The integrated circuit has a total 2n stacked chips where “n” is the number of bonding cycles. This method uses the minimum number of bonding steps and shorter cycle times to fabricate 3DIC since each bonding of an individual chip or chip stack uses single side bonding. The insulating layers are made of a multilayer oxide having at least one chemically activated, ultra-smooth bonding surface capable of bonding to another surface without any external force. This surface bonding technology, combined with the minimized number of bonds, lowers the cost of manufacturing the 3D stacked circuits.