The trend toward miniaturization of electronic products necessitates smaller and more densely packed semiconductor structures. This has resulted in a demand for semiconductor packages which are relatively low loss, lightweight structures and which support increased electronic capabilities like increased density, mobility, and operational life. One solution to this demand is multilayer semiconductor structures or 3D integrated circuits. Fabricating these structures has been a costly and inefficient process since drilling through the insulator substrate can cause fracture and the final semiconductor product generally has worse performance than the 2D integrated circuit. Current 3D fabrication techniques have low processing speeds, high manufacturing costs, and take exorbitant amounts of time to create. The present devices and method promotes reduced cycle times, cost-effective stacking alternatives and increased circuit efficiency.