A miniaturized 3DIC integrated electronic package has multiple functional sections attached to each other through oxide bonding where each section can have single or multiple layers. Micro vias confined within opposing layers, interconnect between layers of each functional section. The vias may have variable diameter from top to bottom to maximize space efficiency. The 3DIC package can also be attached to multi-chip modules through microbumps or pillar technology. Instead of microbumps, a third via can be used to make electrical connection between two stacks where the third via is a high CTE metal with equal or larger size and pitch than the second micro via. The materials stack-up for each functional section may vary but at least one functional section will contain one active transistor layer and two local interconnect routing layers for each active transistor layer. The bonding of multiple functional sections allows the mixture of III-V transistors with Silicon CMOS, for example.