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The presented technology reduces interconnect width, allowing a reduced pitch in comparison to conventional semiconductor structures and devices. This is accomplished with a semiconductor structure composed of a substrate, interconnect pad, and an isolating layer where one or more conductive structure projecting from the surface of an interconnect pad form a connection for electrically and mechanically coupling the semiconductor structure to other semiconductor structures and devices. The electrical connections may be made by drilling holes through the substrate in appropriate locations and plating the inside of the holes with a conducting material (e.g., copper). The interconnect pad is provided to promote scalability of the semiconductor structure since it can couple to other semiconductor structures or devices. An isolating layer includes a polymer, which may be used as a dielectric bridge for crossover of circuits within the same layer of substrate. This dielectric bridge may be created by selective deposition of a dielectric material (e.g., nanoporous silica, silicon oxyfluoride) using physical or chemical vapor deposition. Openings in the isolating layer may be formed by an additive or subtractive process which accommodates one or more conductive structures that fits between the interconnect pad and isolating layer. These processing conditions are cheaper and less bulky than conventional methods of reducing pitch size.