This technology uses a silicon on insulator (SOI) substrate. During co-integration of GaN with 200 mm hybrid SOI, patterned regions are created such that <111> Si is exposed. The depth and coverage of the patterned region cannot exceed 1.5 µm and 50%, respectively, because it will create large stresses during GaN growth on the Si. The SOI substrate thickness is typically in the range of 725-775 µm and corresponds to that used by Si CMOS industry. The invention demonstrates how the current collapse can be reduced to <10% even with <1.5 µm GaN HEMT structure in the patterned region.