The dominant GaN device architecture today is the lateral High Electron Mobility Transistor (HEMT) heterostructure. However, the lateral GaN HEMT device architecture has two key limitations. First, careful management of electric field profiles in the lateral dimension between contacts is required, particularly in high voltage applications. Substantial gate/drain lateral spacing must be maintained to allow high breakdown voltage, which reduces the effective current density. Second, thermal management is complicated by the fact that all current flow is confined to a relatively thin portion of the device near the top surface. In contrast, a vertical GaN device architecture could overcome these limitations because high electric fields occur between contacts on the bottom and top of the structure in the vertical dimension only.